1. Technical Field of the Invention
This invention pertains to reducing storage read access latency. In particular, this invention improves latency by speculatively accessing storage and overlapping data bus access with status determination.
2. Background
The access time of requested data from storage, that is the latency associated with either operand or instruction access, affects the performance of any processor performing such requests.
Storage requests which require more than one machine cycle to evaluate and post status to determine whether main storage should be accessed, contribute to the access time of the requested data.
Requests which must cross shared buses also contribute to data access latency since use of the bus must be requested and granted prior to the transmission of the request and request's data.
One approach to reducing storage read request latency is to provide an owned status memory for tracking whether data in main memory is owned by main memory or by cache. This allows access to main memory to occur simultaneously with access to cache when main memory is owned by main memory. Then, when cache status (hit or miss) is determined, if main memory is owned by main memory and the data accessed simultaneously with cache access, the main memory data is available for transfer to a data bus immediately upon cache miss status being signaled. This approach to overlapping cache and memory access to reduce latency requires the addition of the owned status memory, which contributes to the cost and complexity of the memory controller function.
It is an object of the invention to improve storage access latency.
It is a further object of the invention to improve storage access latency during read operations.
It is a further object of the invention to reduce storage access latency by obtaining control of a data bus substantially simultaneously with availability to that data bus of data read from storage.
It is a further object of the invention to improve storage access latency by speculatively accessing storage pending status determination.
It is a further object of the invention to reduce control logic complexity and reduce busy time of the processor data bus while obtaining control of the data bus substantially simultaneously with availability of data from storage.
It is a further object of the invention to reduce control logic complexity by enabling simultaneous access to main memory and cache memory without the necessity of maintaining an owned status memory.